Job Description
Join Astera Lab’s ASIC team as Design Verification Intern focusing on high-performance compute and networking standards.
Responsibilities
Design and verify blocks using leading edge methodology and tools.
Collaborate with team members on silicon engineering projects.
Utilize RTL design languages and tools for verification tasks.
Analyze and debug design issues to ensure quality outcomes.
Qualifications
Completed 3rd year of study with a minimum GPA of 3.5.
Strong background in Computer or Electrical/Electronic Engineering.
Hands-on knowledge of RTL design languages like Verilog and System Verilog.
Familiarity with scripting languages such as Python or Perl.
Preferred
Knowledge of high-speed interfaces like PCIe and DDR.
Familiarity with Synopsys EDA tools and digital communications courses.
